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82562et 10/100 mbps platform lan connect (plc) networking silicon datasheet product features ieee 802.3 10base-t/100base-tx compliant physical layer interface ieee 802.3u auto-negotiation support digital adaptive equalization control link status interrupt capability xor tree mode support 3-port led support (speed, link and activity) 10base-t auto-polarity correction lan connect interface diagnostic loopback mode 1:1 transmit transformer ratio support low power (less than 300 mw in active transmit mode) reduced power in ?unplugged mode? (less than 50 mw) automatic detection of ?unplugged mode? 3.3 v device 48-pin shrink small outline package revision 1.4 november 2006 free datasheet http:///
datasheet revision history revision revision date description 0.55 sept. 1999 initial release. 0.6 nov. 1999 ? corrected figure 4 ?nrz to mlt-3 encoding diagram on pg. 11 to reflect correct signal transitions. removed ?10base-t error detection and reporting? section since the 82562 does not do 10base-t error reporting. updated bit 13 of table 3 ?register 16 (10 hexadecimal): plc status, con- trol and address data? to reflect correct values. 1.0 may 2000 advance information datasheet release (intel secret). modified table 1 ?82562et hardware configuration? to add one row for xor tree and include column for comments. updated the descrition of the activity led signal in section 3.6, ?led pins?. revised section 3.7, ?miscellaneous cont rol pins? to reflect references to table 1 ?82562et hardware configuration?. updated section 6.0, ?electrical and timing specifications?. replaced diagrams in section 7.1, ?package information?. 1.1 june 2000 advance information datasheet release (intel confidential). on cover page, replaced boundary scan support with xor tree mode support. added bullet for lan connect i/f. pg. 3, added a solution block diagram as included in or-2338 pg. 4 but replaced em with et in diagram. pg. 11, removed figure 4, ?nrz to mlt-3 encoding diagram?. pg. 35, changed the rev. number on the 82562 pinout symbol to 1.0. 1.2 oct 2001 removed confidential status. removed sections: ?physical layer interface functionality? and ?platform lan connect?. changed ?electrical and timing specifications? section to ?voltage and temperature specifications? and removed timing specifications. 1.3 march 2003 added product ordering code in section 1.0. 1.4 nov 2006 corrected the testen signal description. information in this document is provided in connection with intel? products. no license, express or implied, by estoppel or oth erwise, to any intellectual property rights is granted by this document. except as provided in intel's terms and conditions of sale for such products, inte l assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel? products including liabi lity or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property r ight. intel products are not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." int el reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. the 82562et plc may contain design defects or errors known as errata which may cause the product to deviate from published spec ifications. current characterized errata are available on request. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an ordering number and are referenced in this document, or other intel literature may be obtaine d by calling 1-800- 548-4725 or by visiting intel' s website at http://www.intel.com. copyright ? 2006, intel corporation intel? is a trademark or registered trademark of intel corporation or its subsidiaries in the united states and other countries . * other brands and names are the property of their respective owners.
datasheet iii networking silicon ? 82562et contents 1.0 introduction................................................................................................................ ......... 1 1.1 overview ............................................................................................................... 1 1.2 features ................................................................................................................ 1 1.3 references ............................................................................................................ 1 1.4 product code ........................................................................................................2 2.0 82562et architectural overview........................................................................................ 3 3.0 82562et signal descriptions ............................................................................................. 5 3.1 signal type definitions ......................................................................................... 5 3.2 twisted pair ethernet (tpe) pins ......................................................................... 5 3.3 external bias pins ................................................................................................ 5 3.4 clock pins ............................................................................................................ 6 3.5 platform lan connect interface pins.................................................................... 6 3.6 led pins ..............................................................................................................7 3.7 miscellaneous control pins .................................................................................. 7 3.8 power and ground connections .......................................................................... 8 4.0 physical layer interface functionality................................................................................ 9 4.1 100base-tx mode ............................................................................................... 9 4.1.1 100base-tx transmit blocks .................................................................9 4.1.2 100base-tx receive blocks ................................................................11 4.2 10base-t mode .................................................................................................12 4.2.1 10base-t transmit blocks ....................................................................12 4.2.2 10base-t receive blocks .....................................................................13 4.3 analog references..............................................................................................14 4.4 dynamic reduced power & auto plugging detection.........................................14 4.4.1 auto plugging detection.........................................................................14 4.4.2 dynamic reduced power.......................................................................15 4.4.3 configuration ..........................................................................................15 4.5 reset ...................................................................................................................15 4.6 lan connect interface ........................................................................................16 4.6.1 lan connect clock ................................................................................16 4.6.2 lan connect reset................................................................................16 4.7 led functionality ...............................................................................................16 5.0 platform lan connect registers .....................................................................................17 5.1 medium dependent interface registers 0 through 7...........................................17 5.1.1 register 0: control register bit definitions ...........................................17 5.1.2 register 1: status register bit definitions ............................................18 5.1.3 register 2: phy identifier register bit definitions ................................19 5.1.4 register 3: phy identifier register bit definitions ................................19 5.1.5 register 4: auto-negotiation advertisement register bit definitions ....20 5.1.6 register 5: auto-negotiation link partner ability register bit definitions . 20 5.1.7 register 6: auto-negotiation expansion register bit definitions ..........20 5.2 medium dependent interface registers 8 through 15.........................................21
82562et ? networking silicon iv datasheet 5.3 medium dependent interface registers 16 through 31 ...................................... 21 5.3.1 register 16: phy status and control register bit definitions .............. 21 5.3.2 register 17: phy unit special control bit definitions ........................... 22 5.3.3 register 18: phy address register ....................................................... 23 5.3.4 register 19: 100base-tx receive false carrier counter bit definitions 23 5.3.5 register 20: 100base-tx receive disconnect counter bit definitions ... 23 5.3.6 register 21: 100base-tx receive error frame counter bit definitions . 23 5.3.7 register 22: receive symbol error counter bit definitions .................. 24 5.3.8 register 23: 100base-tx receive premature end of frame error counter bit definitions 24 5.3.9 register 24: 10base-t receive end of frame error counter bit defini- tions 24 5.3.10 register 25: 10base-t transmit jabber detect counter bit definitions .. 24 5.3.11 register 27: phy unit special control bit definitions ........................... 24 6.0 electrical and timing specifications................................................................................. 27 6.1 absolute maximum ratings ................................................................................ 27 6.2 dc characteristics ............................................................................................. 27 6.2.1 x1 clock dc specifications ................................................................... 27 6.2.2 lan connect interface dc specifications ............................................. 28 6.2.3 led dc specifications .......................................................................... 28 6.2.4 10base-t voltage and current dc specifications ............................... 28 6.2.5 100base-tx voltage and current dc specifications .......................... 29 6.3 ac characteristics .............................................................................................. 30 6.3.1 10base-t normal link pulse (nlp) timing parameters ..................... 30 6.3.2 auto-negotiation fast link pulse (flp) timing parameters ................. 31 6.3.3 100base-tx transmitter ac specifications ......................................... 32 6.3.4 reset (rstsync) ac specifications ................................................... 32 7.0 package and pinout information ...................................................................................... 33 7.1 package information ........................................................................................... 33 7.2 pinout information ............................................................................................... 34 7.2.1 82562et pin assignments .................................................................... 34 7.2.2 82562et shrink small outlying package diagram ............................... 35
networking silicon ? 82562et datasheet 1 1.0 introduction 1.1 overview the intel ? 82562et is a highly-integrated platform lan connect device designed for 10 or 100 mbps ethernet systems. it is based on th e ieee 10base-t and 100base-tx standards. the ieee 802.3u standard for 100base-tx defines networking over two pairs of category 5 unshielded twisted pair cable or type 1 shielded twisted pair cable. the 82562et complies with the ieee 802.3u auto-negotiation standard and the ieee 802.3x full duplex flow control standard. the 82563et al so includes a phy interface compliant to the current platform lan connect interface. 1.2 features ieee 802.3 10base-t/100base-tx compliant physical layer interface ieee 802.3u auto-negotiation support digital adaptive equalization control link status interrupt capability xor tree mode support for board testing 3-port led support (speed, link and activity) 10base-t auto-polarity correction diagnostic loopback mode 1:1 transmit transformer ratio support low power (less than 300 mw in active transmit mode) reduced power in ?unplugged mode? (less than 50 mw) automatic detection of ?unplugged mode? 3.3 v device 48-pin shrink small outline package platform lan connect interface support 1.3 references ieee 802.3 standard for local and metropolitan area networks, institute of electrical and electronics engineers 82555 10/100 mbps lan phys ical layer interface datasheet, intel corporation lan connect interface specifi cation, intel corporation
82562et ? networking silicon 2 datasheet 1.4 product code the product ordering code for the 82562et is: da82562et.
networking silicon ? 82562et datasheet 3 2.0 82562et architectural overview the 82562et is a highly integrated platform l an connect device that combines a 10base-t and 100base-tx physical layer interfaces. the 82562 et supports a single interface fully compliant with the ieee 802.3 standard. figure 1 provides a block diagram of the 82562et architecture. the 8252et is a 3.3 v device in a 48-pin shrink small outline package (ssop). this document describes the architecture of the device in all modes of operation. four pins, test enable (testen), test clock (isol_tck), test input (isol_ti), and test execute (isol_ex), define the ge neral operation of the device. table 1 shows the pin settings for the different modes of operation. note: combinations not shown in table 1 are reserved and should not be used. figure 1. 82562et block diagram equalizer & blw correction crs/link 10 detection digital clock recovery (100) digital clock recovery (10) digital equalizer adaptation 100base-tx pcs transmit dac 10/100 clock generator rdn/rdp tdn/ tdp lan connect interface port led drivers liled actled speedled auto- negotiation control registers 10base-t pcs mdi/mdi-x 3 3 lan_rstsync lan_txd[2:0] lan_rxd[2:0] lan_clk bias & band- gap voltage circuit x2 x1 crystal 25 mhz table 1. 82562et hardware configuration mode of operation testen isol_tck isol_ti isol_ex comments normal operating mode 0 0 0 0 the isol_tck, isol_ti, and isol_ex pins can remain floating. isolate mode (tri-state and full power-down mode) 0111 the device is in tri-state and power-down mode. 1111 the device is in tri-state and the fully powered down. xor tree 1000 the xor tree is used for board testing and tri-state mode.
82562et ? networking silicon 4 datasheet figure 2. 82562et solution overview control procesor vrm clock addr data ctrl termination addr data ctrl ich2 2 rimm modules mch 82562et plc ide primary amc97 audio/ modem usb port 2 usb port 1 ide secondary pci connector 1 pci connector 3 pci connector 2 pci control bus pci address/data bus 82550 lan controller game conn parallel floppy mouse keyboard serial 1 sio ultradma/33 usb ac97 link lpc bus address/data
networking silicon ? 82562et datasheet 5 3.0 82562et signal descriptions 3.1 signal type definitions 3.2 twisted pair ethernet (tpe) pins 3.3 external bias pins type name description i input input pin to the 82562et. o output output pin from the 82562et. i/o input/output multiplexed input and output pin to and from the 82562et. mlt multi-level analog i/o multi-level analog pin used for input and output. bbias bias pin used for ground connection thr ough a resistor or an external voltage reference. dps digital power supply digital power or ground pin for the 82562et. aps analog power supply analog power or ground pin for the 82562et. pin name pin number type description tdp tdn 10 11 mlt transmit differential pair. the transmit differential pair sends serial bit streams to the unshielded twisted pair (utp) cable. the differential pair is a two-level signal in 10base-t (manchester) mode and a three-level signal in 100base-tx mode (mlt-3). these signals directly interface with the isolation transformer. rdp rdn 15 16 mlt receive differential pair. the receive differential pair receive the serial bit stream from an unshielded twisted pair (utp) cable. the differential pair is a two-level signal in 10base-t mode (manchester) or a three-level signal in 100base-tx mode (mlt-3). these signals directly interface with an isolation transformer. pin name pin number type description rbias10 4 b bias reference resistor 10. this pin should be connected to a 549 ? pull-down resistor. a a. 549 ? for rbias10 is only a recommended value and should be fine tuned for various designs. rbias100 5 b bias reference resistor 100. this pin should be connected to a 619 ? pull-down resistor. b b. 619 ? for rbias100 is only a recommended value and should be fine tuned for various designs.
82562et ? networking silicon 6 datasheet 3.4 clock pins 3.5 platform lan connect interface pins pin name pin number type description x1 46 i crystal input clock. x1 and x2 can be driven by an external 25 mhz crystal of 50 ppm or better. otherwise, x1 is driven by an external metal- oxide semiconductor (mos) level 25 mhz oscillator when x2 is left floating. x2 47 o crystal output clock. x1 and x2 can be driven by an external 25 mhz crystal of 50 ppm or better. pin name pin number type description lan_clk 39 o lan connect clock. the lan connect clock is driven by the 82562et on two frequencies depending on operation speed. when the 82562et is in 100base-tx mode, lan_clk drives a 50 mhz clock. otherwise, lan_clk drives a 5 mhz clock for 10base-t. the lan_clk does not stop during normal operation. lan_ rstsync 42 i reset/synchronize. this is a multiplexed pin and is driven by the media access control (mac) layer device. its functions are: reset. when this pin is a sserted beyond one lan connect clock period, the 82562et uses this signal reset. to ensure reset of the 82562et, the reset signal should remain active for at least 500 seconds. synchronize. when this pin is activated synchronously, for only one lan connect clock period, it is us ed to synchronize the mac and phy on lan connect word boundaries. lan_ txd[2:0] 45, 44, 43 i lan connect transmit data. the lan connect transmit pins are used to transfer data from the mac device to the 82562et. these pins are used to move transmitted data and real time control and management data. they also transmit out of band control data from the mac to the phy. the pins should be fully synchronous to lan_clk. lan_ rxd[2:0] 37, 35, 34 o lan connect receive data. the lan connect receiv e pins are used to transfer data from the 82562et to the mac device. these pins are used to move received data and real time control and management data. they also move out of band control data from the phy to the mac. these pins are synchronous to lan_clk.
networking silicon ? 82562et datasheet 7 3.6 led pins 3.7 miscellaneous control pins pin name pin number type description liled# 27 o link integrity led. the led is active low and the link integrity led pin indicates link status in either 10base-t or 100base-tx mode. if a link is present in either mode, the liled is asserted. actled# 32 o activity led. the led is active low and the activity led signal indicates either receive or transmit activity. when no activity is present, the led is off. the activity led will flicker when activity is present. the flicker rate depends on the activity load. the individual address led control bit (word a hexadecimal, bit 4) in the ich2 eeprom can select the actled# behavior. it controls the activity led (actled) functionality in wake on lan (wol) mode. 0 = in wol mode, the actled is activated by the transmission and reception of broadcast and individual address match packets. 1 = in wol mode, the actled is activated by the transmission and reception of individual address match packets only. this bit is configured by the oem and is activated by a transmission and reception of individual address match packets. spdled# 31 o speed led. the led is active low and the speed led signal indicates the speed of operation, either 10 mb ps or 100 mbps. the speed led is on during 100base-tx operation and off in 10base-t mode. pin name pin number type description adv10 41 i advertise 10 mbps only. the advertise 10 mbps only signal is asserted high, and the 82562et advertises only 10base-t technology during auto-negotiation processes in this state. otherwise, the 82562et advertises all of its technologies. note: adv10 has an internal pull-down resistor. isol_tck 30 i test clock. the test clock signal sets the device into asynchronous test mode in conjunction with the test input, test execute and test enable pins (refer to table 1, ?82562et hardware configuration? on page 3 ). in the manufacturing test mode, it acts as the test clock. note: isol_tck has an internal pull-down resistor. isol_ti 28 i test input. the test input signal sets the device into asynchronous test mode in conjunction with the test clock, test execute and test enable pins (refer to table 1, ?82562et hardware configuration? on page 3 ). in the manufacturing test mode, it acts as the test data input pin. note: isol_ti has an internal pull-down resistor.
82562et ? networking silicon 8 datasheet 3.8 power and ground connections isol_tex 29 i test execute. the test execute signal sets the device into asynchronous test mode in conjunction with the test clock, test input, and test enable pins (refer to table 1, ?82562et hardware configuration? on page 3 ). in the manufacturing test mode, it places the command that was entered through the ti pin in the instruction register. note: isol_tex has an internal pull-down resistor. tout 26 o test output. the test output pin is used for boundary xor scan output. in the manufacturing test mode, it acts as the test output port. testen 21 i test enable. the test enable pin is used to enable test mode and should be externally pulled up to v cc to enable xor tree test mode. pin name pin number type description vcc vccp vcca vcca2 vcct 1, 25 36, 40 2, 7, 9, 12, 14, 17 dps digital 3.3 v power. these pins should be connected to the main digital power supply. vss vssp vssa vssa2 8, 13, 18 24, 48 33, 38 3 6 dps digital ground. these pins should be connected to the main digital ground. vccr 19, 23 aps analog power. vssr 20, 22 aps analog ground. these pins should not be isolated from the main digital. pin name pin number type description
networking silicon ? 82562et datasheet 9 4.0 physical layer interface functionality the 82562et is designed to work in data terminating equipment (dte) mode only. it supports a direct glueless interface to all components that comply with the lan connect specification. the following figure shows how the 82562et plc can be used in a 10/100 mbps ethernet switch design. 4.1 100base-tx mode 4.1.1 100base-tx transmit blocks the transmit subsection of the 82562et accepts 3 bit wide data from the lan connect unit. another subsection passes data unconditionally to the 4b/5b encoder. the 4b/5b encoder accepts nibble-wide data (4 bi ts) from the csma unit and compiles it into 5- bit-wide parallel symbols. these symbols are scramb led and serialized into a 125 mbps bit stream, converted by the analog transmit driver into a mlt-3 waveform format, and transmitted onto the unshielded twisted pair (utp) or shielded twisted pair (stp) wire. 4.1.1.1 100base-tx 4b/5b encoder the 4b/5b encoder complies with the ieee 802.3u 100base-tx standard. four bits are encoded according to the transmit 4b/5b lookup table. the lookup table matches a 5-bit code to each 4-bit code. the table below illustrate s the 4b/5b encoding scheme associated with the given symbol. table 2. 4b/5b encoder figure 3. 82562et 10/100 mbps ethernet solution i/o control hub 2 (ich2) lan controller 82562et (lan connect device) transmit differential pair (tdp/tdn) receive differential pair (rdp/rdn) system bus interface magnetics symbol 5b symbol code 4b nibble code 0 11110 0000 1 01001 0001 2 10100 0010 3 10101 0011 4 01010 0100 5 01011 0101
82562et ? networking silicon 10 datasheet 4.1.1.2 100base-tx scrambler and mlt-3 encoder data is scrambled in 100base-tx in order to reduce electromagnetic emissions during long transmissions of high-frequency data codes. the scrambler logic accepts 5 bits from the 4b/5b encoder block and presents the scrambled data to the mlt-3 encoder. the 82562et implements the 11-bit stream cipher scrambler as adopted by the ansi xt3t9.5 committee for utp operation. the cipher equation used is: x[n] = x[n-11] + x[n-9] (mod 2) the mlt-3 encoder receives the scrambled non-re turn to zero (nrz) data stream from the scrambler and encodes the stream into mlt-3 for presentation to the driver. mlt-3 is similar to nrz1 coding, but three levels are output instead of two. the three output levels are positive, 6 01110 0110 7 01111 0111 8 10010 1000 9 10011 1001 a 10110 1010 b 10111 1011 c 11010 1100 d 11011 1101 e 11100 1110 f 11101 1111 i 11111 inter packet idle symbol (no 4b) j 11000 1st start of packet symbol 0101 k 10001 2nd start of packet symbol 0101 t 01101 1st end of packet symbol r 00111 2nd end of packet symbol and flow control v 00000 invalid v 00001 invalid v 00010 invalid v 00011 invalid h 00100 invalid v 00101 invalid v 00110 invalid v 01000 invalid v 01100 invalid v 10000 flow control s v 11001 invalid symbol 5b symbol code 4b nibble code
networking silicon ? 82562et datasheet 11 negative and zero. when an nrz ?0? arrives at the input of the encoder, the last output level is maintained (either positive, negative or zero). when an nrz ?1? arrives at th e input of the encoder, the output steps to the next level. the order of steps is negative-zero-positive-zero which continues periodically. refer to ieee 802.3 specification for details. 4.1.1.3 100base-tx transmit framing the 82562et does not differentiate between the fi elds of the mac frame containing preamble, start of frame delimiter, data and cyclic redundancy check (crc). the 82562 encodes the first byte of the preamble as the ?jk? symbol, encode s all other pieces of data according to the 4b/5b lookup table, and adds the ?tr? code after th e end of the packet. the 82562 scrambles and serializes the data into a 125 mbps stream, enco des it as mlt-3, and drives it onto the wire. 4.1.1.4 transmit driver the transmit differential lines ar e implemented with a digital slope controlled current driver that meets twisted pair physical media device (tp-pm d) specifications. current is sunk from the isolation transformer by the transmit differential pins. the conceptual transmit differential waveform for 100 mbps is illustrated in the following figure. figure 4. conceptual transmit differential waveform the magnetics module external to the 82562et converts i tdp and i tdn to 2.0 v pp , as required by the tp-pmd specification. the sa me magnetics used for 100base-tx mode can also work in 10base-t mode. 4.1.2 100base-tx receive blocks the receive subsection of the 82562et accepts 100base-tx mlt-3 data on the receive differential pair. due to the adva nced digital signal processing design techniques employed, the 82562et will accurately receive valid data from category 5 (cat5) utp and type 1 stp cable of length well in excess of 100 meters. 4.1.2.1 adaptive equalizer the distorted mlt-3 signal at the end of the wi re is restored by the equalizer. the equalizer performs adaptation based on the shape of the received signal, equalizing the signal to meet superior data dependent jitter performance.
82562et ? networking silicon 12 datasheet 4.1.2.2 receive clock and data recovery the clock recovery circuit uses ad vanced digital signal processing technology to compensate for various signal jitter causes. the circuit recovers the 125 mhz clock and data and presents the data to the mlt-3 decoder. 4.1.2.3 mlt-3 decoder, descrambler, and receive digital section the 82562et first decodes the mlt-3 data, and then the descrambler reproduces the 5b symbols originated in the transmitter. the descrambling is based on synchronization to the transmission of the 11-bit linear feedback shift register (lfsr) duri ng an idle phase. the data is decoded at the 4b/5b decoder. after the 4b symbols are obtained , the 82562et outputs the receive data to the csma unit. in 100base-tx mode, the 82562et can detect errors in receive data in a number of ways. any of the following conditions is considered an error: link integrity fails in the middle of frame reception. the start of stream delimiter ?jk? symbol is not fully detected after idle. an invalid symbol is detected at the 4b/5b decoder. idle is detected in the middle of a frame (before ?tr? is detected). 4.2 10base-t mode 4.2.1 10base-t transmit blocks 4.2.1.1 10base-t manchester encoder after the 2.5 mhz clocked data is serialized in a 10 mbps serial stream, the 20 mhz clock performs the manchester encoding. the manchester code always has a mid-bit transition. the boundary transition occurs only when the data is the same from bit to bit. for example, if the value is 11b, then the change is from low to high within the boundary. 4.2.1.2 10base-t driver and filter since 10base-t and 100base-tx have different filtration needs, both filters are implemented inside the chip. the 82562et supports both technologies through one pair of transmit differential pins and by externally sharing the same magnetics. in 10 mbps mode the line drivers use a pre-distortion algorithm to improve jitter tolerance. the line drivers reduce their drive level during the second half of ?wide? (100 ns) manchester pulses and maintain a full drive level during all narrow (50 ns) pulses and the first half of the wide pulses. this reduces line overcharging during wide pulses, a major source of jitter.
networking silicon ? 82562et datasheet 13 4.2.2 10base-t receive blocks 4.2.2.1 10base-t manchester decoder the 82562et performs manchester decoding and timing recovery in 10base-t mode. the manchester encoded data stream is decoded from the receive differential pair. this data is transferred to the controller at 2.5 mhz/nibble . the high-performance circuitry of the 82562et exceeds the ieee 802.3 jitter requirements. 4.2.2.2 10base-t twisted pair ethernet (tpe) receive buffer and filter in 10 mbps mode, data is expected to be receive d on the receive differential pair after passing through isolation transformers. the filter is implemented inside the 82562et for supporting single magnetics that are shared with the 100base-tx si de. the input differential voltage range for the twisted pair ethernet (tpe) receiver is greater th an 585 mv and less than 3.1 v. the tpe receive buffer distinguishes valid receive data, link test pulses, and the idle condition, according to the requirements of the 10base-t standard. the following line activity is determined to be inactive and is rejected as invalid data: differential pulses of peak magnitude less than 300 mv. continuous sinusoids with a differential amplitude less than 6.2 v pp and frequency less than 2 mhz. sine waves of a single cycle duration starting with 0 or 180 phase that have a differential amplitude less than 6.2 v pp and a frequency of at least 2 mhz and not more than 16 mhz. these single-cycle sine waves are discarded only if they are preceded by 4 bit times (400 ns) of silence. all other activity is determined to be either data, link test pulses, auto-negotiation fast link pulses, or the idle condition.
82562et ? networking silicon 14 datasheet 4.3 analog references the 82562et has two inputs, rbias100 and rbias10, that require external resistor connections to set biases for its internal analog section. the input pins are sensitive to the resistor value and experimentation is required to determine the correct values for any given layout. resistors of 1% tolerance should be used. 4.4 dynamic reduced power & auto plugging detection the 82562et can be configured to support a dynamic reduced power mode. this mode reduces power consumption of the 82562et when lan activity is not present. the reduced power mode decreases power consumption from 300 mw to about 50 mw and is based on automatic detection of cable plugging. if the 82562et is configured to support dynamic power reduction, it enters the reduced power mode whenever a cable is not conn ected to the device. in reduced power mode, the 82562et shuts off the link circuits, except the circuit used for the automatic plugging detection. on the lan connect side, the entire interface rema ins active, including full access to all mii management interface (mmi) registers. in this mode, the 82562et switches to the 10 mbps speed interface (5 mhz for lan connect). thus, the reduced power mode is fully transparent to driver. 4.4.1 auto plugging detection the 82562et senses the link all the time. if it det ects loss of any link activity for more than 6.6 seconds, it indicates to the media access controlle r (mac) an ?unplugged state? by resetting the sql lan connect control bit. if the 82562et is in reduced power mode and link activity is detected, the 82562et notifies the mac (in less than 1 second) that it is in a ?plugged state? by setting the sql lan connect control bit. link activity detection is based on energy detection. figure 5. analog references 82562 rbias100 rbias10 619 1% 549 1%
networking silicon ? 82562et datasheet 15 4.4.2 dynamic reduced power the 82562et can be configured to support dynamic reduced power. in the dynamic reduced power mode, the 82562et transitions to reduced power mo de when an unplugged state is detected. the 82562et will only return to full power if the reduced power bit on the lan connect is reset and a plugged state is detected. however, if the 82562et is not configured to support dynamic reduced power, the 82562et operates according to the l an connect power-down bit (in other words, the 82562et will operate in reduced power mode only if the lan connect power-down bit is set). 4.4.3 configuration the dynamic reduced power mode is configured through bit 13 of register 16. the default value is disabled (0). the status of the 82562et can be read through bits 10:9 of register 16. when the 82562et is in reduced power mode, these two bits are set to 1b. the 82562et can enter a reduced power state manually through bit 11 of register 0. this bit is ored with the lan connect power down bit, whic h allows the 82562et to enter a reduced power state. 4.5 reset when 82562et?s reset signal (rstsync) is asse rted for at least 500 seconds, all internal circuits are reset. the 82562et can also be reset through the mii management register reset bit (register 0, bit 15). table 3. register 16 (10 hexadecimal): plc status, control and address data bit name description read/write 13 dynamic reduced power down 0 = automatic reduced power down enabled 1 = automatic reduced power down disabled (default) read/write 10 100base-tx power down the 100base-tx power down bit indicates the power state. 0 = normal operation (default) 1 = power down read only 9 10base-t power down the 10base-t power down bit indicates the power state. 0 = normal operation (default) 1 = power down read only table 4. register 0: control data bit name description read/write 11 reduced power down 0 = reduced power down disabled (normal operation; default) 1 = reduced power down enabled read/write
82562et ? networking silicon 16 datasheet 4.6 lan connect interface the 82562et supports the lan connect interf ace as specified in the lan connect interface specification. the lan connect is the i/o contro l hub 2 (ich2) interface to the 82562et. the 8- pin interface incorporates all mii and mii mana gement functionality and includes the reset functionality as well. 4.6.1 lan connect clock the 82562et drives a 50 mhz or 5 mhz clock to the mac depending on the selected technology (100base-tx or 10base-t, respectively). the 82562et does not stop the lan connect clock for any reason. during reduced power mode, the 82562et drives a 5 mhz clock. 4.6.2 lan connect reset to determine the type of signal on the plc reset/synchronization pin, the 82562et filters out pulses that are less than 200 nanoseconds. to reset the 82562et, the pulse should be longer than 500 seconds. 4.7 led functionality table 5. led functionality led driver function description actled# activity the driver blinks at a rate related to the utilization. the blinking occurs during transmission or reception of a frame. spdled# speed the driver is low for 100base-tx operation and high for 10base-t mode. liled# link valid the driver is lo w when a valid link is present.
networking silicon ? 82562et datasheet 17 5.0 platform lan connect registers the following subsections describe phy regist ers that are accessible through the lan connect management frame protocol. acronyms mentioned in the registers are defined as follows: sc: self cleared. ro: read only. rw: read/write. e: eeprom setting affects content. ll: latch low. lh: latch high. 5.1 medium dependent interface registers 0 through 7 5.1.1 register 0: control register bit definitions bit(s) name description default r/w 15 reset this bit sets the status and control register of the phy to their default states and is self-clearing. the phy returns a value of one until the reset process has completed and accepts a read or write transaction. 0 = normal operation 1 = phy reset 0rw sc 14 loopback this bit enables loopback of transmit data nibbles to the receive data path. the phy receive circuitry is isolated from the network. note that this may cause the descrambler to lose synchronization and produce 560 nanoseconds of ?dead time.? note also that the loopback configuration bit takes priority over the loopback mdi bit. 0 = loopback disabled (normal operation) 1 = 1 = loopback enabled 0rw 13 speed selection this bit is valid on read and controls speed when auto- negotiation is disabled. 0 = 10 mbps 1 = 100 mbps 1rw 12 auto-negotiation enable this bit enables auto-negotiation. bits 13 and 8, speed selection and duplex mode, respectively, are ignored when auto-negotiation is enabled. 0 = auto-negotiation disabled 1 = auto-negotiation enabled 1rw 11 reduced power down this bit sets the phy into a low power mode. 0 = power down disabled (normal operation) 1 = power down enabled 0rw
82562et ? networking silicon 18 datasheet 5.1.2 register 1: status register bit definitions 10 isolate this bit allows the phy to isolate the medium independent interface. the phy is disconnected from the lan connect block on both the transmit and receive side. 0 = normal operation 1 = isolates internal medium independent interface 0rw 9 restart auto- negotiation this bit restarts the auto-negotiation process and is self- clearing. 0 = normal operation 1 = restart auto-negotiation process 0rw sc 8 duplex mode this bit controls the duplex mode when auto-negotiation is disabled. when auto-negotiation is enabled this bit is read only and always equals 1b. when the phy is placed in loopback mode, the behavior of the phy shall not be affected by the status of this bit. 0 = half duplex 1 = full duplex 0rw/ ro 7 collision test this bit is not used in the 82562et and has a default value of 1b. (if it is used in other devices, it forces a collision in response to the assertion of the transmit enable signal.) 1rw 6:0 reserved these bits are reserved and should be set to 0000000b. 0 rw bit(s) name description default r/w 15 reserved this bit is reserved and should be set to 0b. 0 ro 14 100base-tx full-duplex this bit enables 100base- tx full-duplex operation and is dependent on adv10. if adv10 is active, the default value is 0. 0 = phy unable to perform full-duplex 100base-tx 1 = phy able to perform full-duplex 100base-tx 1ro 13 100 mbps half- duplex this bit enables 100base-tx half-duplex operation and is dependent on adv10. if adv10 is active, the default value is 0. 0 = phy unable to perform half-duplex 100base-tx 1 = phy able to perform half-duplex 100base-tx 1ro 12 10 mbps full- duplex this bit enables 10base-t full duplex operation. 0 = phy unable to perform full-duplex 10base-t 1 = phy able to perform full-duplex 10base-t 1ro 11 10 mbps half- duplex this bit enables 10base-t half-duplex operation. 0 = phy unable to perform half-duplex 10base-t 1 = phy able to perform half-duplex 10base-t 1ro 10:7 reserved these bits are reserved and should be set to 0000b. 0 ro bit(s) name description default r/w
networking silicon ? 82562et datasheet 19 5.1.3 register 2: phy identifier register bit definitions 5.1.4 register 3: phy identifier register bit definitions 6 management frames preamble suppression this bit allows the 82562et to receive management frames with suppressed preamble. 0 = phy will not accept management frames with preamble suppressed 1 = phy will accept management frames with preamble suppressed 0ro 5 auto-negotiation complete this bit reflects status of the auto-negotiation process. 0 = auto-negotiation process has not completed 1 = auto-negotiation process completed 0ro 4 remote fault 0 = no remote fault condition detected 1 = remote fault condition detected 0ro 3 auto-negotiation ability this bit reflects the phy?s auto-negotiation ability status. 0 = phy is unable to perform auto-negotiation 1 = phy is able to perform auto-negotiation 1ro 2 link status this bit reflects link status. 0 = invalid link detected 1 = valid link established 0ro ll 1 jabber detect this bit is used only in 10base-t mode. 0 = no jabber condition detected 1 = jabber condition detected 0ro lh 0 extended capability this bit enables the extended register capabilities. 0 = extended register capabilities disabled 1 = extended register capabilities enabled 1ro bit(s) name description default r/w 15:0 phy id (high byte) value: 02a8 hexadecimal -- ro bit(s) name description default r/w 15:0 phy id (low byte) value: 0330 hexadecimal -- ro bit(s) name description default r/w
82562et ? networking silicon 20 datasheet 5.1.5 register 4: auto-negotiation ad vertisement register bit definitions 5.1.6 register 5: auto-negotiation link partner ability register bit definitions 5.1.7 register 6: auto-negotiation ex pansion register bit definitions bit(s) name description default r/w 15 next page this bit is a constant 0, transmit primary capability data page. 0ro 14 reserved this bit is reserved and should be set to 0b. 0 ro 13 remote fault 0 = no remote fault 1 = indicate link partner?s remote fault 0rw 12:5 technology ability field technology ability field is an 8-bit field containing information indicating supported technologies specific to the selector field value. 0010 1111 rw 4:0 selector field the selector field is a 5-bit field identifying the type of message to be sent by auto-negotiation. this field is read only and contains a value of 00001b, ieee standard 802.3. 00001 ro bit(s) name description default r/w 15 next page this bit reflects the phy?s link partner?s next page ability. -- ro 14 acknowledge this bit is used to indicate that the 82562et has successfully received its link partner?s auto- negotiation advertising ability. -- ro 13 remote fault this bit reflects the phy?s link partner?s remote fault condition. -- ro 12:5 technology ability field this bit reflects the phy?s link partner?s technology ability field. -- ro 4:0 selector field this bit reflects the phy?s link partner?s selector field. -- ro bit(s) name description default r/w 15:5 reserved these bits are reserved and should be set to 0. 0 ro 4 parallel detection fault this bit clears itself on read. 0 = no fault detected via parallel detection 1 = fault detected via parallel detection (multiple link fault occurred) 0ro sc lh 3 link partner next page able 0 = link partner is not next page able 1 = link partner is next page able 0ro
networking silicon ? 82562et datasheet 21 5.2 medium dependent interface registers 8 through 15 registers eight through fifteen are reserved for ieee. 5.3 medium dependent interface registers 16 through 31 5.3.1 register 16: phy status and control register bit definitions 2 next page able 0 = 0 = local drive is not next page able 1 = local drive is next page able 0ro 1 page received this bit clears itself on read. 0 = new page not received 1 = new page received 0ro sc lh 0 link partner auto- negotiation able 0 = link partner is not auto-negotiation able 1 = link partner is auto-negotiation able 0ro bit(s) name description default r/w bit(s) name description default r/w 15:14 reserved these bits are reserved and should be set to 00b. 00 rw 13 reduced power down disable this bit disables the automatic reduced power down. 0 = enable automatic reduced power down 1 = disable automatic reduced power down 1rw 12 reserved this bit is reserved and should be set to 0b. 0 rw 11 receive de- serializer in-sync indication this bit indicates status of the 100base-tx receive de-serializer in-sync. -- ro 10 100base-tx power-down this bit indicates the power state of 100base-tx phy unit. 0 = normal operation 1 = power-down 1ro 9 10base-t power-down this bit indicates the power state of 10base-t phy unit. 0 = normal operation 1 = power-down 1ro 8 polarity this bit indicates 10base-t polarity. 0 = normal polarity 1 = reverse polarity -- ro 7 reserved this bit is reserved and should be set to 0b. 0 ro
82562et ? networking silicon 22 datasheet 5.3.2 register 17: phy unit special control bit definitions 6:2 phy address these bits contain the sampled phy address. -- ro 1 speed this bit indicates the auto-negotiation result. 0 = 10 mbps 1 = 100 mbps -- ro 0 duplex mode this bit indicates the auto-negotiation result. 0 = half-duplex 1 = full-duplex -- ro bit(s) name description default r/w 15 scrambler by- pass 0 = normal operations 1 = by-pass scrambler 0rw 14 by-pass 4b/5b 0 = normal operation 1 = 4 bit to 5 bit by-pass 0rw 13 force transmit h- pattern 0 = normal operation 1 = force transmit h-pattern 0rw 12 force 34 transmit pattern 0 = normal operation 1 = force 34 transmit pattern 0rw 11 valid link 0 = normal operation 1 = 100base-tx valid link 0rw 10 symbol error enable 0 = normal operation 1 = symbol error output is enabled 0rw 9 carrier sense disable this bit controls the rece ive 100 carrier sense disable function. 0 = carrier sense enabled 1 = carrier sense disabled 0rw 8 disable dynamic power-down 0 = dynamic power-down enabled 1 = dynamic power-down disabled 0rw 7 auto-negotiation loopback 0 = auto-negotiation normal mode 1 = auto-negotiation loopback 0rw 6 mdi tri-state 0 = normal operation 1 = mdi tri-state (transmit driver tri-states) 0rw 5 force polarity 0 = normal polarity 1 = reversed polarity 0rw 4auto polarity disable 0 = normal polarity operation 1 = auto polarity disabled 0rw 3 squelch disable 0 = normal squelch operation 1 = 10base-t squelch test disable 0rw bit(s) name description default r/w
networking silicon ? 82562et datasheet 23 5.3.3 register 18: phy address register 5.3.4 register 19: 100base-tx r eceive false carri er counter bit definitions 5.3.5 register 20: 100bas e-tx receive disconnect counter bit definitions 5.3.6 register 21: 100base-tx r eceive error frame counter bit definitions 2 extended squelch 1 = 10base-t extended squelch control enabled 0 = 10base-t extended squelch control disabled 0rw 1 link integrity disable 0 = normal link integrity operation 1 = link disabled 0rw 0 jabber function disable 0 = normal jabber operation 1 = jabber disabled 0rw bit(s) name description default r/w 15:5 reserved these bits are reserved and should be set to a constant 0. 0ro 4:0 phy address these bits are set to the phy?s address. 00001 ro bit(s) name description default r/w 15:0 receive false carrier these bits are used for the false carrier counter. -- ro sc bit(s) name description default r/w 15:0 disconnect event this field contains a 16-bit counter that increments for each disconnect event. the counter stops when it is full and self-clears on read -- ro sc bit(s) name description default r/w 15:0 receive error frame this field contains a 16-bi t counter that increments once per frame for any receive error condition (such as a symbol error or premature end of frame) in that frame. the counter stops when it is full and self-clears on read. -- ro sc bit(s) name description default r/w
82562et ? networking silicon 24 datasheet 5.3.7 register 22: rece ive symbol error count er bit definitions 5.3.8 register 23: 100base-tx receive premature end of frame error counter bit definitions 5.3.9 register 24: 10bas e-t receive end of frame error counter bit definitions 5.3.10 register 25: 10base-t tran smit jabber dete ct counter bit definitions 5.3.11 register 27: phy unit sp ecial control bit definitions bit(s) name description default r/w 15:0 symbol error counter this field contains a 16-bit counter that increments for each symbol error. the counter stops when it is full and self-clears on read. in a frame with a bad symbol, each sequential six bad symbols count as one. -- ro sc bit(s) name description default r/w 15:0 premature end of frame this field contains a 16-bit counter that increments for each premature end of frame event. the counter stops when it is full and self-clears on read. -- ro sc bit(s) name description default r/w 15:0 end of frame counter this is a 16-bit counter that increments for each end of frame event. the counter stops when it is full and self-clears on read. -- ro sc bit(s) name description default r/w 15:0 jabber detect counter this is a 16-bit counter that increments for each jabber detection event. the counter stops when it is full and self-clears on read. -- ro sc bit(s) name description default r/w 15:6 reserved these bits are reserved and should be set to a constant 0. 0ro 5 switch probe mapping this bit switches the ma pping on the leds. the led mapping is described below in bits 2:0, led switch control. this bit should always be set to 0b. 0rw
networking silicon ? 82562et datasheet 25 4 reserved this bit is reserved and should be set to 0. 0 ro 3 100base-tx receive jabber disable this bit enables the carrier sense disconnection while the phy is in jabber mode at 100 mbps speed. 0rw 2:0 led switch control value 000 001 010 011 100 101 110 111 actled activity speed speed activity off off on on liled link collision link collision off on off on 000 rw bit(s) name description default r/w
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networking silicon ? 82562et datasheet 27 6.0 electrical and timing specifications 6.1 absolute maximum ratings maximum ratings are listed below: case temperature under bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 c to 135 c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 c to 150 c supply voltage with respect to v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 v to 3.45 v output voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.50 v to 3.45 v input voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v cc to 3.45 v stresses above the listed absolute maximum ratings may cause permanent damage to the 82562et device. this is a stress rating only and functional operations of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 6.2 dc characteristics 6.2.1 x1 clock dc specifications notes: 1. this characteristic is only characterized, not tested. it is valid for digital pins only. table 6. general dc specifications symbol parameter condition min typical max units notes v cc supply voltage 3.0 3.3 3.45 v t temperature minimum/maximum case temperature 085c p power consumption 10/100mbps (transmitter on) 300 mw reduced power 50 mw auto-negotiation 200 mw table 7. x1 clock dc specifications symbol parameter condition min typical max units notes v il input low voltage 0.8 v v ih input high voltage 2.0 v i ilih input leakage currents 0 < v in < v cc 10 a c i input capacitance 8pf 1
82562et ? networking silicon 28 datasheet 6.2.2 lan connect interf ace dc specifications notes: 1. this characteristic is only characterized, not tested. it is valid for digital pins only. 6.2.3 led dc specifications 6.2.4 10base-t voltage and current dc specifications notes: current is measured between the transmit di fferential pins (tdp and tdn) at 3.3 v. 1. r l is the resistive load measured across the transmit differential pins, tdp and tdn. table 8. lan connect interface dc specifications symbol parameter condition min typical max units notes v ccj input/output supply voltage 3.0 3.45 v v il input low voltage -0.5 0.3v ccj v v ih input high voltage 0.6v ccj v ccj + 0.5 v i il input leakage current 0 < v in < v ccj 10 a v ol output low voltage i out = 1500 a 0.1v ccj v v oh output high voltage i out = -500 a 0.9v ccj v c in input pin capacitance 8pf 1 table 9. led dc specifications symbol parameter condition min typical max units notes v olled output low voltage i out = 10 ma 0.7 v v ohled output high voltage i out = -10 ma 2.4 v table 10. 10base-t transmitter symbol parameter condition min typical max units notes v od10 output differential peak voltage r l = 100 ? 2.2 2.8 v 1
networking silicon ? 82562et datasheet 29 notes: 1. the input differential resistance is measured across the receive differential pins, rdp and rdn. 6.2.5 100base-tx voltage and current dc specifications notes: current is measured between the transmit differential pins (tdp and tdn) at 3.3 v. 1. r l is the resistive load measured across the transmit differential pins, tdp and tdn. notes: 1. the input differential resistance is measured across the receive differential pins, rdp and rdn. table 11. 10base-t receiver symbol parameter condition min typical max units notes r id10 input differential resistance dc 10 k ? 1 v ida10 input differential accept peak voltage 5 mhz f 10 mhz 585 3100 mv v idr10 input differential reject peak voltage 5 mhz f 10 mhz 300 mv v icm10 input common mode voltage v cc/2 v table 12. 100base-tx transmitter symbol parameter condition min typical max units notes v od100 output differential peak voltage r l = 100 ? 0.95 1.0 1.05 v 1 table 13. 100base-tx receiver symbol parameter condition min typical max units notes r id100 input differential resistance dc 10 k ? 1 v ida100 input differential accept peak voltage 500 1200 mv v idr100 input differential reject peak voltage 100 mv v icm100 input common mode voltage v cc/2 v
82562et ? networking silicon 30 datasheet 6.3 ac characteristics figure 6 defines the conditions for timing measurements. the design must guarantee proper operation for voltage swings and slew rates that exceed the specifi ed test conditions. 6.3.1 10base-t normal link pu lse (nlp) timing parameters figure 6. ac test level conditions table 14. normal link pulse timing parameters symbol parameter condition min typical max units notes t6 t nlp_wid nlp width 10 mbps 100 ns t7 t nlp_per nlp period 10 mbps 8 16 24 ms input levels 1.4 v output levels v oh = 2.0 v v ol = 0.8 v figure 7. normal link pulse timings normal link pulse t7 t6
networking silicon ? 82562et datasheet 31 6.3.2 auto-negotiation fast link pulse (flp) timing parameters table 15. fast link pulse timing parameters symbol parameter condition min typical max units notes t8 t f lp_wid flp width (clock and data) 100 ns t9 t flp_clk_clk clock pulse to clock pulse period 111 125 139 s t10 t flp_clk_data clock pulse to data pulse period 55.5 62.5 69.5 s t11 t flp_bur_num pulses in one burst 17 33 # t12 t flp_bur_wid burst width 2 ms t13 t flp_bur_per flp burst period 8 16 24 ms figure 8. fast link pulse timings fast link pulse t10 t8 t9 clock pulse data pulse clock pulse flp bursts t12 t13
82562et ? networking silicon 32 datasheet 6.3.3 100base-tx transmitter ac specifications 6.3.4 reset (rstsync) ac specifications table 16. 100base-tx transmitter timing parameters symbol parameter condition min typical max units notes t14 t jit tdp/tdn differential output peak jitter hls data 1400 ps table 17. reset timing parameters symbol parameter condition min typical max units notes t58 t rst_wid reset pulse width 500 s t59 t pop_rst power-up to falling edge of reset 1000 s figure 9. reset timing parameters power up (vcc) reset t59 t58
networking silicon ? 82562et datasheet 33 7.0 package and pinout information 7.1 package information the 82562et is a 48-pin shrink small outlying package (ssop). the package dimensions are shown in figure 10 . more information on intel device packaging is available in the intel packaging handbook, which is available from the intel literature center or your local sales office. figure 10. dimension diagram for the 82562et 48-pin ssop
82562et ? networking silicon 34 datasheet 7.2 pinout information 7.2.1 82562et pin assignments table 18. 82562et pin assignments pin number pin name pin number pin name pin number pin name pin number pin name 1 vcc 13 vss 25 vcc 37 lan_rxd2 2 vcca 14 vcct 26 tout 38 vssp 3 vssa 15 rdp 27 liled 39 lan_clk 4 rbias10 16 rdn 28 isol_ti 40 vccp 5 rbias100 17 vcct 29 isol_tex 41 adv10 6 vssa2 18 vss 30 isol_tck 42 lan_rstsync 7 vcca2 19 vccr 31 spdled 43 lan_txd0 8 vss 20 vssr 32 actled 44 lan_txd1 9 vcct 21 testen 33 vssp 45 lan_txd2 10 tdp 22 vssr 34 lan_rxd0 46 x1 11 tdn 23 vccr 35lan_rxd147 x2 12 vcct 24 vss 36 vccp 48 vss
networking silicon ? 82562et datasheet 35 7.2.2 82562et shrink small outlying package diagram figure 11. 82562et pin out diagram 82562et pin diagram ssop48 rev 1.0 top view 1 2 6 5 4 3 7 8 9 10 11 12 13 14 15 16 17 32 33 37 36 35 34 38 39 40 41 42 43 44 45 46 47 48 vssr (aps) vccr (aps) vcct (aps) vss (dps) vss (dps) vssa (aps) rbias10 (b) rbias100 (b) vssa2 (aps) vcca2 (aps) tdp (mlt) vcca (aps) lan_txd2 (i) lan_rxd2 (o) lan_rstsync vssp (dps) x1(i) x2 (o) vss (dps) adv10 (i) isol_ti (i) 18 19 20 21 22 23 24 31 30 29 28 27 26 25 liled# (o) actled# (o) spdled# (o) tdn (mlt) vcct (aps) rdp (mlt) rdn (mlt) vcct (aps) vccr (aps) vssr (aps) vcct (aps) vss (dps) vss (dps) vcc (dps) lan_txd1 (i) lan_txd0 (i) lan_rxd1 (o) lan_rxd0 (o) vccp (dps) lan_clk (o) vccp (dps) vssp (dps) vcc (dps) pin types: aps = analog power supply, dps = digital power supply, i = input, o = output isol_tex (i) tout (o) isol_tck (i) testen (i)
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